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Course Outline

The course covers the origins of the RISC-V architecture, including the modular architecture definition comprising base architectures and extensions. It details the RISC-V ISA, focusing on registers and the instruction set, along with features aligned with modern software concepts and an overview of RISC-V implementations.
The curriculum also addresses the RISC-V system architecture, specifically examining exceptions and their handling mechanisms, such as the CLIC interrupt controller and the ECLIC interrupt controller within the GD32VF103.

Practical Exercises:
1. Firmware development for the GD32VF103 using VScode.
2. Managing interrupts on the GD32VF103.

Requirements

A foundational understanding of the C programming language is required.

 7 Hours

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