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Course Outline
RISC-V Architecture Basics and Ecosystem Overview
RISC-V ISA Landscape and Industry Adoption
- The open ISA philosophy and the RISC-V International standardization framework
- Core RISC-V concepts: Load-Store architecture, register files, and byte ordering
- Comparing RISC-V with ARM, x86, and POWER: trade-offs in heterogeneous computing
- Ecosystem maturity: SiFive, T-Head, Western Digital, and the expanding open-source silicon community
- Standard interfaces: RISC-V Privileged ISA and the Machine Software Abstraction Layer (MSBL)
Memory Models and ABI Compliance
- Unprivileged Architecture specs: CSR maps, exception handling, and memory hierarchies
- RV32I / RV64I instruction sets and ABI compliance for cross-platform binary portability
- Memory ordering conventions and barrier instructions for multiprocessor systems
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Base integer (I), Multiply/Divide (M), and Atomic (A) extensions
- Bitness-aware strategies for 32-bit and 64-bit RISC-V targets
- Calling conventions and stack frame management for embedded and real-time systems
Compiler Toolchain Proficiency
- LLVM-based toolchain: Clang, LLVM, and Binutils for RISC-V cross-compilation
- Linker scripts, sections, and memory layout for bare-metal and RTOS environments
- Compiler intrinsics, optimization levels, and profiling-driven tuning
- Open-source toolchain workflows: building, testing, and packaging custom GCC/Clang toolchains
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Rust systems programming for RISC-V: zero-cost abstractions, unsafe memory management, and bare-metal dev
- No-Std environments: custom linkers, device drivers, and memory-mapped I/O
- Zephyr RTOS and Buildroot BSP development for RISC-V targets
- Peripheral interfacing: GPIO, I2C, SPI, UART, and DMA controllers
Power and Performance Optimization
- Clock gating, power domain management, and low-power optimization
- Cycle-accurate performance analysis using simulation profilers and hardware counters
- Tuning real-time interrupt latency for safety-critical apps
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- OpenSBI (SBI spec implementation): bootloader firmware development
- UEFI/EDK II on RISC-V: modern firmware boot stack development
- Coreboot and U-Boot porting for RISC-V single-board computers
Linux Kernel Integration
- Mainline RISC-V kernel contributions: device tree overlays, CPU topology, and AIA interrupt controller drivers
- Vendor BSP development and kernel configuration for custom SoC platforms
- File systems, networking stacks, and containerization (Docker, Kubernetes) on RISC-V hosts
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Network-on-Chip (NoC) design methods for RISC-V multi-core processors
- AXI4/CHI cache coherence and inter-processor communication protocols
- Open-source IP integration: OpenCores, ChIPS Framework, and vendor RTL components
- Bus matrix design and memory controller integration (DDR, SRAM, eMMC, PCIe)
FPGA-Based Processor Prototyping
- FPGA synthesis and implementation of RISC-V cores (e.g., BOOM, VexRiscv, PULP)
- SystemVerilog Assertions (SVA) and UVM-based functional verification
- Formal verification tools and property-based testing for core validation
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Vector load/store, VFMA, and matrix computation acceleration
- Variable-length vector operations (VL, VLEN) for workload-optimized SIMD execution
- Vector masks, segment control, and data type flexibility for DSP and ML workloads
Custom DSP and Domain-Specific Instruction Design
- Designing domain-specific accelerators via custom extensions and CBAR-based operand interfaces
- Compiler frontend mods for custom instruction generation and code emission
- Hardware-software partitioning for accelerator integration in production SoCs
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- NPU architecture: systolic arrays, tensor cores, and weight compression for on-chip AI
- Model quantization (INT8, INT4, FP8) for edge deployment on RISC-V
- Framework support: TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V
Heterogeneous Computing for AI Workloads
- Co-design of RISC-V host CPU and AI accelerator NPU for real-time inference
- Memory subsystem optimization: HBM/DDR bandwidth for ML weights and activations
- Thermal and power budgeting for edge AI inference systems
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Physical Memory Protection (PMP) and Page Table walker security mechanisms
- Secure Enclave/TEE architectures for RISC-V: OP-TEE integration, SEV-class trusted execution
- Boot chain security: root of trust, secure boot, and measured launch attestation
Cryptographic Acceleration
- RISC-V crypto extensions (Zk, Zkr, K): SHA, AES, RSA, RSA-PSS, and ECC acceleration
- Post-quantum cryptography (PQC) integration for next-gen RISC-V processors
- Side-channel attack mitigation: constant-time programming, masking, and hardware RNGs
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- ISA extension design: encoding, tables, ABI impact, and RISC-V International submission
- Custom register file design with CBAR for operand dispatch
- Instruction pipelining, hazard detection, and pipeline mods for custom extensions
Verification and Signoff of Custom Architecture Modifications
- Testbench design for custom extensions: directed vs. constraint-random stimulus
- Regression testing and coverage-driven verification for architectural changes
- Interoperability testing: ensuring custom instructions work within ABI constraints
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- ISO 26262 functional safety compliance for RISC-V automotive processors
- ASIL-Q classification and safety manual development for RISC-V silicon IP
- Deterministic interrupt handling, lockstep cores, and memory protection for safety-critical systems
Industrial Real-Time and Edge Computing Applications
- IEC 61508 SIL compliance and deterministic scheduling on RISC-V multicore platforms
- Industrial IoT gateway development: connectivity, edge analytics, and OTA updates
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Architecture specification: ISA extensions and core configuration for a defined use case
- RTL implementation in SystemVerilog with UVM testbenches and formal verification
- FPGA prototyping, boot firmware dev, and bare-metal driver integration
- Linux BSP and toolchain customization for the custom RISC-V core
- AI workload deployment: NPU integration, quantization, and benchmarking
- Security validation: PMP enforcement, secure boot, and crypto acceleration benchmarks
- Technical documentation, IP strategy analysis, and cross-functional team presentation
Requirements
None.
21 Hours
Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
That we could you real life examples
